The subject matter relates to semiconductor devices and more particularly to semiconductor memory devices with an improved method for transferring addresses.
A semiconductor memory device may include millions or billions of memory cells to be accessed. Generally, all memory cells of the semiconductor memory device are arranged in a matrix for effective addressing that is called a cell area. Each cell of the matrix is crossed by a word line and a bit line. Thus, each memory cell can be accessed by a selected word line and a selected bit line in a cell area of the matrix. The semiconductor memory device decodes a row address and a column address transferred from a memory controller to select a word line and a bit line in the cell area. The semiconductor memory device receives a row address and a column address through address pads, and receives or outputs data through data pads. Typically, the data pads and the address pads require relatively a large region in a chip area of the semiconductor memory device. To reduce the number of pads, the semiconductor memory device receives the row address and the column address through a common address pad.
In order to store more data in a semiconductor memory device, memory cells are designed as small as design technology for manufacturing a semiconductor device allows. Because of that, a data signal stored in a memory cell is very small, and is not sufficient to directly use as an output data. Hence, a data signal stored in a memory cell is transferred to and amplified by an amplifying circuit because the magnitude of the data signal is very small. Further, an original data signal stored in the memory cell may be destroyed during the transferring and amplifying process. Thus, after the amplified data signal is output externally, the data signal amplified by the amplifying circuit should be restored into the selected memory cell. Because of the amplifying time and the restoring time, the semiconductor memory device can not continuously output data, although a memory controller seeks continuous data from the semiconductor memory device. After one data is output externally, a latency time, caused by the amplifying time and the restoring time, occurs prior to externally outputting a next data.
To reduce the latency time, recent designs of semiconductor memory devices have at least two or more banks. Each bank of such a semiconductor memory device includes a group of memory cells and can independently access its own memory cells. While one bank externally outputs a data, another bank prepares to externally output a next data. Because the banks can alternatively output data, the memory controller can continuously receive a plurality of data from the semiconductor memory device without latency time. In the semiconductor memory device with a plurality of banks, a bank should be selected to access a memory cell. Thus, the semiconductor memory device with the plurality of banks receives not only a row and a column address, but also a bank address from the memory controller. The semiconductor memory device selects one of banks using the bank address, and then at least one cell of the selected bank is chosen by the row address and the column address. The memory controller can continuously receive data from the semiconductor memory device if the bank address is selected alternately.
FIG. 1 is a block diagram of a conventional semiconductor memory device having a plurality of banks. As shown, the semiconductor memory device includes an address input unit 100, a command decoding unit 120, a plurality of address transferring units 190A to 190H, and a plurality of banks, i.e., first bank, comprising BANK00, BANK10, BANK20, and BANK30 to eighth bank, comprising BANK07, BANK17, BANK27, and BANK37. The address input unit 100 receives a bank address BANK_ADD<3Bit> and a row address ADD<12Bit> to generate a bank selecting signal BANKT<0:7> and an internal row address ROW_ADD<0:11>. The command decoding unit 120 generates a row pulse signal ROWP in response to an active command signal ACT. The address transferring units 190A to 190H transfer the internal row address ROW_ADD<0:11> to the plurality of banks in response to the row pulse signal ROWP.
Each bank in the semiconductor memory device is divided into four bank blocks. That is, one bank is separated into four bank blocks, and each bank block is arranged in a respective area of which is called a quarter bank area. For example, a first bank is composed of the four bank blocks BANK00, BANK10, BANK20, and BANK30. Because there are eight banks in the example shown in FIG. 1, each of the quarter bank areas 140, 150, 160, and 170 includes eight bank blocks. Once a command for data access is input to the semiconductor memory device, one of the eight banks is first selected and a predetermined amount of data, e.g., 16 or 32 bits of data, is output from the selected bank. In case of 16-bit data output, each bank block outputs 4 bits of data through corresponding data pads. Typically, data pads are arranged at each side a memory circuit area. As the distance between the selected bank and data pads becomes shorter, data from the selected bank can be more quickly output externally. To reduce the distance between a selected bank and the data pads, each bank is separated to four bank blocks, with each bank block arranged in a respective quarter bank area as shown.
A bank block of eight bank blocks in each quarter bank area 140 to 170 is chosen by the bank select signal BANKT<0:7> in response to the row pulse signal ROWP. At least one memory cell is chosen by the internal row address ROW_ADD<0:11> in each of the chosen bank blocks. A data access occurs at the chosen memory cell. The row pulse signal ROWP from the command decoding unit 120 is a control signal for announcing that the internal row address ROW_ADD<0:11> is generated. Whenever the row pulse signal ROWP is generated, each of the address transferring units 190A to 190H transfers the internal row address ROW_ADD<0:11> to corresponding bank blocks of 32 bank blocks BANK00 to BANK37. For instance, the address transferring unit 190A transfers the internal row address ROW_ADD<0:11> to corresponding bank blocks BANK00 to BANK03 of the first quarter bank area 140 in response to the row pulse signal ROWP.
FIG. 2 is a schematic diagram showing a part of the address transferring unit 190A in FIG. 1. The address transferring units 190A to 190H share substantially the same configuration. Therefore, for the sake of convenience, the part of the address transferring unit 190A is shown and explained as an example of the address transferring units 190A to 190H, and the diagram of the other address transferring units 190B to 190H are omitted. The address transferring unit 190A includes a transmission gate TG for transferring an internal address signal ROW_ADD<0> in response to the row pulse signal ROWP and a latch unit 191 for latching an output of the transmission gate TG to output an internal row address ROW_ADDI<0>. The address transferring unit 190A includes also another eleven transmission gates and another eleven latch units for transferring and latching the other internal address signals ROW_ADD<1:11>. For the sake of convenience, the another eleven transmission gates and eleven latch units are not shown in FIG. 2.
FIG. 3 is a timing diagram showing an operation for transferring the internal row address ROW_ADD<0:11> to the bank blocks in the four quarter bank areas. Whenever the row pulse signal ROWP is pulsed from the command decoding unit 120, one of the bank selecting signals BANKT<0:7> is enabled by the address input unit 100 and activates corresponding bank blocks. The internal row address ROW_ADDI<0:11> is transferred into each bank in response to the row pulse signal ROWP. Each bank block is enabled in response to a corresponding one of the bank selecting signals BANKT<0:7>, and at least one memory cell of the enabled bank block is selected by the internal row address ROW_ADDI<0:11>. For example, once the bank selection signal BANKT1 is enabled, the internal row address ROW_ADDI<0:11> is transferred to the 32 bank blocks in response to the row pulse signal ROWP and the four bank blocks BANK01, BANK 11, BANK 21, and BANK31 are enabled. If the bank selection signal BANKT5 is enabled, the internal row address ROW_ADDI<0:11> is transferred to the 32 bank blocks in response to the row pulse signal ROWP and the four bank blocks BANK05, BANK15, BANK25, and BANK35 are enabled.
Although only one of the bank selecting signals BANKT<0:7> is enabled at a time, the internal row address ROW_ADDI<0:11> is transferred into all of the bank blocks. Because the address transferring units 190A to 190H do not receive any signal having information for which of eight banks is selected, the address transferring units 190A to 190H transfer the internal row address ROW_ADDI<0:11> to all bank blocks. Whenever the row pulse signal ROWP is pulsed, each bank blocks receives the internal row address ROW_ADDI<0:11> and determines whether the received internal row address ROW_ADDI<0:11> is used in response to its respective bank selecting signal.
According to the semiconductor memory device in FIG. 1, whenever the row pulse signal ROWP is pulsed, the internal row address ROW_ADDI<0:11> is transferred to all of the bank blocks, and each bank block determines whether the transferred internal row address ROW_ADDI<0:11> is used or not. However, most of the bank blocks do not need to be enabled, except the four bank blocks corresponding to each of the bank selecting signals BANKT<0:7>. In other words, the internal row address is transferred to bank blocks that do not need to use the internal row address ROW_ADDI<0:11> and each of the bank blocks makes its own determination as to whether the transferred internal row address ROW_ADDI<0:11> is used or not. As a result, the semiconductor memory device should consume unnecessary current because all of the bank blocks are maintained an enabled state. As the number of the banks or memory cells included in a semiconductor memory device increases, the unnecessarily consumed current may become more significant.